debug-tb
Debug SystemVerilog testbench failures in the SVC project. Use when a testbench fails (make <module>_tb), to analyze CHECK_* assertion failures, watchdog timeouts, or unexpected signal values. Provides systematic debugging workflow using VCD waveforms and failure output analysis.
$ Installer
git clone https://github.com/pbozeman/svc /tmp/svc && cp -r /tmp/svc/docs/skills/debug-tb ~/.claude/skills/svc// tip: Run this command in your terminal to install the skill
